Principal Packaging Engineer – Irvine

-Design and develop custom substrate/module with supporting electrical simulation to reduce cross-talk, IR drop, and noise issues in device-Perform package and PCB design collaboration feasibility study and provide feedback to chip designer during the developmental stage on device floor plan and pad layout to achieve the most cost effective package solution.-Design and Interface with PCB / form factor PCB designer on routing and trade-off analysis of PCB layer stack-up, layer counts and manufacturing technologies based on different pin map assignments and pin depopulation scheme scenarios to achieve the lowest system cost solution. -Define package assembly process, troubleshoot and provide sustaining support on packaging issues. Consult on packaging problems & improvement in packaging process -Work with marketing and chip lead to select packages and define packaging cost and roadmap for new devices -New packaging and process technology development and deployment of the technology in HVM-Work closely with PCB vendors on design rule manufacturing capabilities and future technology roadmaps-Work closely with QA and customer to resolve quality issues -Interface with packaging vendors to identify quality, production and technology capabilities, technology improvement plans and cost reduction goals Requirements:BS/MS/Phd in EE/ME/Physics/Material Science plus 12 + years experience with IC Package Design and PCB Layout Strong authority on Cadence APD/APE, Avanti Design tool, ACAD for custom substrate and module design experience is mustStrong authority on Zuken CR-5000 PCB design tool is must Solid background and hands on experience in Design & Mfg of modules package, substrate and PCBKnowledgeable on PCB design rules and manufacturing technologies for cellular applicationKnowledge with electrical modeling tools such as Speed2000, HFSS, and other related tools. Must have good oral communication and organization skills

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Salary: Negotiable